1. Field of the Invention
The present invention relates to a semiconductor device comprising MOS type field effect transistors (hereinafter referred to as MOS FETs) and, in particular, to a structure and material of the MOS FET.
2. Description of the Related Art
FIG. 8 shows an MOS FET of a background art. As shown in FIG. 8, oxide film 2 is formed on semiconductor substrate 1, and gate electrode 3 is further formed on film 2. At both sides of gate electrode 3, impurities such as boron or arsenic are diffused into substrate 1 so that p-n junctions are formed therebetween. Thereafter, source and drain regions 4 and 5 are formed. Conventionally, a silicon single crystal is used for the substrate of MOS FETs.
FIG. 9 shows another MOS FET of a second background art. As shown in FIG. 9, polysilicon layer 7 is formed on insulating substrate 6, and the MOS FET structure shown in FIG. 8 is further formed on polysilicon layer 7. Such a structure can be adapted to a liquid crystal display device or the like.
In FIG. 9, polysilicon layer 7 is deposited on insulating substrate 6. Gate oxide film 8 and gate electrode 9 are subsequently stacked on polysilicon layer 7. Thereafter, impurities such as boron or arsenic are diffused in both sides of the stacked layer, so that source and drain regions 10 and 11 are formed. Then, an MOS FET structure is obtained wherein a conductive channel forming area is formed by the polysilicon layer which is parallel to the main plane of the substrate.
When the MOS FET of FIG. 9 is used as a circuit element contained in an LSI chip, a problem occurs.
More specifically, when the MOS FET is to be formed, the source and drain regions are obtained by a thermal diffusion of p- or n-type impurities, or by an ion implantation of such impurities. Thereafter, a heat treatment process such as a passivasion film forming process is normally executed to manufacture an LSI chip. Such a heat treatment process, however, invites unintentional diffusion of the impurities at the source and drain regions.
Conventionally, a polysilicon involves grain boundaries at which many dangling bonds and/or many vacancies exist. These dangling bonds and/or vacancies accelerate the speed of a thermal diffusion. (Roughly speaking, a thermal diffusion coefficient of impurities in a polysilicon is several to several tens the number of a thermal diffusion coefficient of impurities in a single crystal silicon.) For this reason, when the distance between the source and the drain becomes small, the source could be short-circuited to the drain by the thermal diffusion in the case of FIG. 9, even if a manufacturing technique ensures no short-circuiting in the case of FIG. 8.
According to a current LSI process, the length of an impurity diffusion in the case of FIG. 8 is an order of about 1000 .ANG.. Consequently, no problem occurs when the distance between the source and the drain is about 1 .mu.m. However, the length of an impurity diffusion in the case of FIG. 9 is an order of about 1 .mu.m, thereby causing the problem of said short-circuiting. This problem cannot be avoided even if insulating substrate 6 of FIG. 9 is made of a single crystal silicon.
As mentioned above, it is hard to reduce the length of a conductive channel forming area formed in a polysilicon of an MOS FET, because a thermal diffusion of impurities of the source and drain regions at the conductive channel forming area is so large. In other words, according to a currently available LSI technique, it is very difficult to minimize the size of an MOS FET along its lateral direction.